The present invention relates to an on-board write art of a program memory built in a single-chip microcomputer serving as a data processor, particularly to an art to be effectively applied to a single-chip microcomputer provided with a flash-type electrically erasable and programmable read only memory (hereafter referred to as a flash-type EEPROM or a flash memory).
A single-chip microcomputer (also known as a microcomputer) serving as a data processor has a built-in program memory for storing an operation program. The single-chip microcomputer executes predetermined data processing specified in the operation program stored in the built-in program memory.
The program memory has been formed with a mask-type nonvolatile memory (hereafter referred to as a mask-type read-only memory or mask ROM) or an electrically programmable nonvolatile memory (hereafter referred to as an electrically programmable read-only memory or EPROM). In recent years, however, a flash-type electrically erasable and programmable read-only memory (hereafter referred to as a flash-type EEPROM or flash memory) has been applied to a program memory.
The flash memory allows written data to be electrically erased or electrically rewritten. Therefore, a microcomputer having a built-in flash memory as a program memory has the following advantages.
Cutover of a software program (application software) developed by a user generally tends to be delayed. Therefore, it is possible to assemble the hardware for a microcomputer-applied system before the cutover of a software program and then write a developed software program in a flash memory of a microcomputer. Thereby, it is possible to quickly ship the microcomputer-applied system.
Moreover, when specification-modified software or function-added software (upgraded software or version-up software) is developed for already shipped application system software, it is possible for a user to rewrite the shipped application system software to the above newly-developed software.
That is, in the case of a microcomputer having a built-in flash memory as a program memory, the microcomputer is assembled on a printed circuit board, mounting board, or system board and then, the processing for writing an operation program in the above flash memory can be performed. In this specification, the processing for programming data in a built-in flash memory after assembling a microcomputer having the built-in flash memory on a printed circuit board, mounting board, or system board is referred to as xe2x80x9con-board programmingxe2x80x9d and this programming mode is referred to as xe2x80x9con-board programming modexe2x80x9d.
Several methods are available to the flash memory programming. These methods are roughly divided into the following two types.
(1) The first method is referred to as a user program mode or boot mode. This mode uses a method for branching the flow of program execution by a central processing unit (CPU) built in a microcomputer to the on-board programming and changing the data in a flash memory by the CPU.
(2) The second method is referred to as a programming mode using a ROM writer. This mode uses a method for changing the data in a flash memory by external means (ROM writer) by stopping a microcomputer.
Japanese Patent Laid-Open No. 180664/1994 discloses a system for handling trouble at the time of rewriting by moving a trouble handling program to another area when rewriting a flash memory.
In the case of the above first method, because the information stored in a built-in flash memory are subject to rewriting, programming control programs present in memories other than a flash memory such as a built-in RAM (random access memory) are executed by a central processing unit (CPU) to erase or program the data in the flash memory.
In the case of the above first method, original functions of a microcomputer are not lost under the erasing or programming state of the flash memory. Therefore, an interrupt to the central processing unit (CPU) erroneously occurs due to a signal input supplied from a unit outside of the microcomputer or an address error occurs while the programming control program is executed. Moreover, because an NMI (Non-Maskable Interrupt) cannot inhibit an interrupt, an unexpected NMI may occur while the data in the flash memory is programmed or erased according to the above first method. A similar state may occur if an interrupt other than the NMI is enabled.
In general, when an interrupt or address error occurs, the processing by a central processing unit is branched to an interrupt handling routine or exception handling routine. A vector address showing the head address of an interrupt handling routine or exception handling routine is used to branch the processing by the central processing unit to the interrupt handling routine or exception handling routine. When an interrupt occurs or exception handling occurs, the vector address of a relative interrupt or exception handling routine is obtained by the central processing unit. The obtained vector address is programmed in a program counter of the central processing unit and the program flow of the central processing unit jumps to an address indicated by the vector address to execute relative interrupt or exception handling.
It is clarified as the result of study by the present inventor that the following is a matter to be cautioned.
That is, a plurality of vector addresses are generally stored in the vector address storage area of a program memory. Even when a flash memory is used as a program memory, the same is applied to the above mentioned and thus, a plurality of vector addresses are stored in the vector address storage area of the flash memory.
However, if an interrupt occurs or exception handling occurs when a flash memory is used as a program memory and erasing or programming is executed for the flash memory in the user program mode or boot mode, a central processing unit cannot obtain a desired vector address stored in the vector address storage area of the flash memory.
That is, vector addresses are present in the program memory, though a rewrite control program for erasing or programming the data in the flash memory in the user program mode or boot mode is present in a memory (e.g. RAM) other than the flash memory. Therefore, no correct vector address can be obtained during erasing or programming for the flash memory serving as the program memory. As a result, it has been clarified that a microcomputer may run away or an application system may be damaged if an interrupt occurs or exception handling occurs in the user program mode or boot mode of a program memory. Moreover, if the microcomputer runs away and data is over-erased from or over-programmed in the flash memory, it may be impossible to reproduce the microcomputer-application system. It is general means to detect trouble such as a power-supply voltage drop by an interrupt such as an NMI.
It is regarded that erasing or programming for the flash memory includes erasing verify operation and programming verify operation.
In the case of a microcomputer having a built-in flash memory as a program memory, a user can program software in the built-in flash memory after assembling the hardware of an application system or rewrite the software stored in the built-in flash memory of a shipped applied system. Therefore, there are a lot of advantages in setting a flash memory in a microcomputer. However, it is found that occurrence of an interrupt or occurrence of exception handling during on-board programming in the user program mode or boot mode of a built-in flash memory may cause a microcomputer to run away or an application system to be damaged.
It is an object of the present invention to improve the safety of a system during on-board programming of a program memory.
It is another object of the present invention to provide a data processor including an electrically erasable and programmable non-volatile memory as a program memory and capable of preventing a microcomputer from running away and from being damaged even when an interrupt handling or exception handling is requested during on-board programming of the above program memory.
It is still another object of the present invention to provide a microcomputer which includes a flash memory as a program memory and can respond to a request for an interrupt handling or exception handling made during on-board programming or erasing of the program memory.
It is still another object of the present invention to provide a single-chip microcomputer which includes a flash memory as a program memory and is constituted so as to be able to obtain a vector address related to the interrupt handling or exception handling to which a central processing unit responds. When an request for an interrupt handling or exception handling is made during on-board programming or erasing of the program memory.
The above and other objects and novel features of the present invention will become more apparent from the description and accompanying drawings of this specification.
The outline of a typical invention among those disclosed in this application is briefly described below.
A data processor comprises an electrically erasable or programmable program memory (18), a central processing unit (12) accessible to the program memory (18), and malfunction exclusion means for excluding a malfunction due to occurrence of an interrupt or occurrence of exception handling while the data in the program memory is erased or programmed.
The malfunction exclusion means can include the following structures.
(1) As shown in FIG. 6, a first control logic circuit (G5) for excluding or invalidating an interrupt request or an exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed is provided in the data processor.
Therefore, because the first control logic circuit (G5) excludes or invalidates the interrupt request or exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed in the user program mode or boot mode, the central processing unit (12) does not execute the operation for obtaining a vector address corresponding to the interrupt request or exception handling request while the data in the program memory (18) is erased or programmed. This improves the safety of a system during on-board programming of the program memory (18). Thereby, it is possible to inhibit an unintended interrupt request from occurring.
(2) As shown in FIG. 7, a second control logic circuit (G6) for stopping erasing or programming of the data in the program memory (18) in response to an interrupt request or exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed in the user program mode or boot mode is provided in the data processor.
That is, while the data in the program memory (18) is erased or programmed, the second control logic circuit (G5) responds to an interrupt request or exception handling request to the central processing unit (12) and stops erasing or programming of the data in the program memory (18). Specifically, the second control logic circuit (G5) changes the data in the control bits such as an erasing control bit (32), a programming control bit (33), and a verifying control bit (34) of an operation control register set to the program memory (18) from active state to inactive state.
Therefore, when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the second control logic circuit (G5) stops erasing or programming of the data in the program memory (18). Occurrence of the above interrupt may be caused by a programming error of a programming and erasing control program or an emergency such as an outage. Therefore, by stopping erasing or programming of the data in the program memory (18), over-erasing or over-programming of data in a flash memory can be prevented. Moreover, thereafter, the central processing unit (12) can obtain a vector address corresponding to the interrupt request or exception handling request from the program memory (18). Thus, improvement of the safety of the system during on-board programming of the program memory (18) is achieved.
(3) As shown in FIGS. 3 and 5, selected memory change means (G1, G2, and G4) for changing a memory selecting operation from the program memory (18) to another memory are provided in the data processor so that a predetermined area of a memory other than the program memory (18) such as a random access memory (13) can be accessed by inhibiting access to the vector address storage area of the program memory (18) when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed. Moreover, the selected memory change means (G1, G2, and G4) can be set to a bus controller (27).
In this case, vector address data for interrupt handling or exception handling to be processed when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed is previously stored in a predetermined area of a memory other than the program memory (18). Moreover, the vector address data stored in the predetermined storage area is set so as to indicate the head address of a predetermined interrupt handling routine or exception handling routine stored in another storage area of the memory other than the program memory (18).
(3.1) In the above Item (3), when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the selected memory change means (G1 and G2) respond to detection of the access to the vector address storage area of the program memory (18) and in activates a selection signal of the program memory (18) Instead, the selected memory change means (G1 and G2) activate a selection signal of the memory (13) other than the program memory (18).
(3.2) In the above Item (3), when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the selected memory change means (G4) responds to detection of the access to the vector address storage area of the program memory (18) and converts an address signal for accessing the vector address storage area of the program memory (18) into an address signal for accessing a predetermined storage area of a memory such as the random access memory (13) other than the program memory (18).
According to the structure shown in the above Item (3.1) or (3.2), the central processing unit (12) can obtain a vector address related to a relative interrupt handling routine or exception handling routine by accessing another area of the memory other than the program memory (18) even if an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed in the user program mode or boot mode. Therefore, over-erasing or over-programming of data in a flash memory can be prevented by using an NMI and thereby, notifying a microcomputer of an emergency such as drop of power supply voltage Vcc due to an outage and stopping erasing or programming of the data in the program memory (18). In this case, it is possible to protect a flash memory from an abnormal state such as over-erasing, over-programming, or intermediate state by executing the processing for recording a stop state of erasing or programming in an interrupt handling routine to an NMI. This achieves the improvement of the safety of a system during on-board programming of the program memory (18).